The important challenge to optimize the double patterning process toward 22nm node and beyond

Historically, lithographic scaling has been driven by both improvements in wavelength and numerical aperture. In the semiconductor industry, the transition to 1.35NA immersion lithography has recently been completed, and the focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh´s definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for various device layouts.