DocumentCode
3501706
Title
Physical IP and advanced SOI design for 22nm SOI technology
Author
Pelloie, Jean-Luc ; Laabidi, Selma ; Charafeddine, Kenza ; Laplanche, Yves
Author_Institution
ARM Grenoble Design Center, Grenoble, France
fYear
2011
fDate
25-27 April 2011
Firstpage
1
Lastpage
2
Abstract
The 22nm CMOS technology node is currently under development at the major semiconductor companies. While the process is being developed and the associated design rules qualified it is important to set in parallel the design infrastructure to enable early circuit design. This paper shows how this has been accomplished through the design of a test chip including a circuit demonstrator.
Keywords
CMOS integrated circuits; integrated circuit design; integrated circuit testing; silicon-on-insulator; CMOS technology node; SOI technology; advanced SOI design; associated design rules; circuit demonstrator; circuit design; design infrastructure; physical IP; semiconductor company; size 22 nm; test chip; Capacitance; History; Libraries; Power demand; Routing; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-8493-5
Type
conf
DOI
10.1109/VTSA.2011.5872266
Filename
5872266
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