Information theoretic capacity of long on-chip interconnects in the presence of crosstalk

This paper presents a framework for calculating the data capacity of long on chip interconnects. This framework is based on the Shannon´s capacity theorem. The extension of this theorem into binary symmetric channels (BSC) is studied and applied to the VLSI interconnects. This paper presents a simulation study that shows the variation of capacity with a variety physical and operating conditions of long wires. The results show that the operating frequency, that was arrived at using a worst case delay analysis, can be vastly increased through use of error correction coding. This capacity can also be used as a benchmark for evaluation of coding schemes on interconnects