Via distribution model for yield estimation

Author

Uezono, Takumi ; Okada, Kenichi ; Masu, Kazuya

Author_Institution

Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama

fYear

2006

fDate

27-29 March 2006

Lastpage

484

Abstract

In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-mum and 0.13-mum CMOS processes, and demonstrate yield degradation caused by vias

Keywords

CMOS integrated circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit yield; 0.13 micron; 0.18 micron; CMOS process; gate-level netlist; track utilization; via distribution; wire-length distribution; yield estimation; Bridge circuits; CMOS technology; Circuit synthesis; Degradation; Etching; Integrated circuit interconnections; Routing; Semiconductor device modeling; Wire; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-2523-7

Type

conf

DOI

10.1109/ISQED.2006.144

Filename

1613182