DocumentCode
3502093
Title
On Parallelizing the CryptMT Stream Cipher
Author
Stefan, Deian ; Nummey, David B. ; Harwayne-Gidansky, Jared ; Dalai, I.L.
Author_Institution
Dept. of Electr. Eng., S*ProCom2, New York, NY
fYear
2008
fDate
11-14 May 2008
Firstpage
1082
Lastpage
1086
Abstract
Fast stream ciphers are used extensively for encrypted data transmission in mobile networks and over multi- gigabit links. CryptMT, a recently proposed stream cipher, is one of the final candidates for standardization by the European Union´s eSTREAM project. Cryptanalysis of CryptMT has discovered no feasible attacks thus far. We present a scalable technique for parallelizing CryptMT and present an area-efficient hardware implementation on a field- programmable gate array (FPGA). On the Xilinx Virtex-2 Pro FPGA, a 2x parallelization delivers throughputs of up to 16 Gbits/s while using minimal logic resources (1,782 slices). This is highly area-efficient compared to implementations of ciphers such as AES. Possibilities for higher degrees of parallelization are also discussed.
Keywords
cryptography; field programmable gate arrays; logic design; CryptMT stream cipher; Xilinx Virtex-2 Pro FPGA; cryptanalysis; field-programmable gate array; minimal logic resources; Cryptography; Data communication; Field programmable gate arrays; GSM; Hardware; Logic; Standardization; Telephony; Throughput; Wireless application protocol;
fLanguage
English
Publisher
ieee
Conference_Titel
Vehicular Technology Conference, 2008. VTC Spring 2008. IEEE
Conference_Location
Singapore
ISSN
1550-2252
Print_ISBN
978-1-4244-1644-8
Electronic_ISBN
1550-2252
Type
conf
DOI
10.1109/VETECS.2008.230
Filename
4525786
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