Effects of copper plating thickness of Ni/Fe alloy leadframe on the thermal performance of Small Outline Transistor (SOT) packages

Small Outline Transistor (SOT) packages, due to their low cost and low profile, are widely used in consumer electronics. Ni/Fe alloy (A42) is the most widely used leadframe material of SOT packages because of its low cost, good formability and CTE (coefficient of thermal expansion) match with silicon die. The very small size of SOT packages allow a higher package density on a board, but the small size and close proximity of SOT packages make thermal management difficult. The low thermal conductivity of A42, which is less than one tenth of that of copper, makes the thermal conduction even more difficult. Thus, the method of copper plating on A42 leadframe is used to enhance thermal conductivity of SOT packages while keeping their low cost and good CTE match between leadframe and silicon die. In this paper, the junction temperature T_j, the junction-to-ambient thermal resistance θ_j-a and the junction-to-solder joint thermal resistance θ_j-sp were used to evaluate the heat dissipating ability of the package. The Finite Element Method was applied to study the influence of copper plating thickness on the thermal performance of a SOT package. Results show that with a thin layer of copper plating, the thermal resistance of the package can be greatly decreased. A thermal resistance circuit model and the corresponding thermal resistance expression on function of the copper plating thickness were then proposed to quantify the influence of copper plating thickness. The proposed expression, which follows a hyperbolic form, can well predict thermal resistance of the model.