Efficiency of adiabatic logic for low-power, low-noise VLSI

Author

Mahmoodi-Meimand, Hamid ; Afzali-Kusha, Ali ; Nourani, Mehrdad

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

Volume

1

fYear

2000

fDate

2000

Firstpage

324

Abstract

The efficiency of a fully adiabatic logic circuit is compared with its combinational and pipelined static CMOS counterparts. The performance of each circuit is studied in terms of the maximum frequency of operation, the minimum voltage of operation, the. circuit energy consumption, and the switching noise generated by the circuit. An 8-bit carry look-ahead adder is designed using a 0.6-μm CMOS technology for all three logic styles. Based on the post-layout simulation results, the adiabatic adder exhibits energy savings of 76% to 87% and 87% to 90% compared to its combinational and pipelined static CMOS counterparts, respectively. It also exhibits a considerable reduction in switching noise, compared to its static CMOS counterparts

Keywords

CMOS logic circuits; VLSI; adders; carry logic; circuit simulation; integrated circuit noise; logic simulation; low-power electronics; 0.6 micron; 8 bit; CMOS technology; adiabatic logic; carry look-ahead adder; circuit energy consumption; energy savings; low-noise VLSI; low-power VLSI; maximum frequency of operation; minimum voltage of operation; post-layout simulation results; switching noise; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Energy consumption; Frequency; Logic circuits; Switching circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951652

Filename

951652