Development of large die assembly process based on simulation and experiments of underfill materials selection

Flip-chip ball grid array (FCBGA) packaging was developed to meet the requirements of high I/O density and high electrical performance and the trend of persistent miniaturization of electronic products. Underfill is usually used in flip-chip packaging to fill the gap between the silicon die and the substrate to provide solder bumps protection, compensation of the coefficient of thermal expansion (CTE) mismatch between the silicon die, the solder bumps, and the organic substrate, and prevent fracture failures such as crack of the solder bumps during thermal cycling. The thermal-mechanical properties of underfill, such as CTE, Tg (glass transition temperature) and Young´s modulus, impact greatly on the reliability of flip-chip packages. This paper presents a study of underfill selection and assembly of large Cu/low-k die (19.2 mm×15.8 mm) with 160 μm bump pitch. Thermal stress simulation was carried out to select suitable underfill material for the Cu/low-k flip chip package. Thermal cycling (TC) test was performed over a range from 125 to -55°C for 1000 cycles to verify the reliability of the package using different underfill materials.