Modified carry skip adder for reducing first block delay

The carry skip adder has low complexity and moderate delays. Within each block, ripple carry is used to produce the sum bits and a carry. When the carry of the first block is generated, skipping produces the next carry with two gate delays per block. The second block cannot pass carry signals until the block generates the first carry. A modified carry skip adder has been designed for reducing the first block delays. Carry lookahead logic is used for the first carry computation. Although the modified carry skip adder uses a few extra gates because of the CIA logic, it provides better speed than the conventional carry skip adder. It certainly works well with fixed-size blocks