Title :
A high throughput FPGA implementation of a bit-level matrix-matrix product
Author :
Amira, A. ; Bouridane, A. ; Milligan, P. ; Sage, P.
Author_Institution :
Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
Abstract :
This paper presents a novel architecture for a matrix-matrix multiplication algorithm. The paper describes the mathematical model for the algorithm (based on Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation requiring (N2) and O(2nN) as area and time complexities respectively, where N is the matrix size and n is the word length
Keywords :
field programmable gate arrays; matrix multiplication; Baugh-Wooley algorithm; FPGA architecture; Xilinx board design; area complexity; bit-level matrix-matrix product; efficiency; mathematical model; matrix-matrix multiplication algorithm; throughput; time complexity; Application software; Computer architecture; Concurrent computing; Discrete Fourier transforms; Discrete cosine transforms; Field programmable gate arrays; Matrix decomposition; Signal processing algorithms; Systolic arrays; Throughput;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951667
