A minimal hardware constrained scheduling algorithm for VLSI design automation

Author

Lin, Chi-Ho

Author_Institution

Dept. of Comput. Sci., Semyang Univ., Chungbuk, South Korea

Volume

2

fYear

1999

fDate

36495

Firstpage

860

Abstract

In this paper, we present a new VHDL intermediate format CDDG (control dominated data graph) and a minimal hardware constrained scheduling algorithm for VLSI design automation. The intermediate format, CDDG, represents the constraints which limit hardware design such as conditional branch, sequential operation and time constraints. The proposed scheduling algorithm could handle the conditional branches effectively and could check the timing constraints efficiently. It minimizes the total operating time by reducing the number of the constraints to be as maximal as possible, searching a few paths produced by conditional branches. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples

Keywords

VLSI; circuit CAD; data flow graphs; hardware description languages; high level synthesis; integrated circuit design; scheduling; timing; VHDL intermediate format CDDG; VLSI design automation; conditional branches; control dominated data graph; hardware design; minimal hardware constrained scheduling algorithm; sequential operation; time constraints; timing constraints; total operating time; Automatic control; Costs; Design automation; Hardware; High level synthesis; Registers; Scheduling algorithm; Time factors; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 99. Proceedings of the IEEE Region 10 Conference

Conference_Location

Cheju Island

Print_ISBN

0-7803-5739-6

Type

conf

DOI

10.1109/TENCON.1999.818554

Filename

818554