Layout generation for low-power NMOS 4-phase dynamic logic array

An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M×N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the NMOS 4-phase dynamic logic