DocumentCode :
3503690
Title :
FPGA implementation of an efficient high-throughput sphere decoder for MIMO systems based on the smallest singular value threshold
Author :
Wu, Xiang ; Thompson, John S.
Author_Institution :
Inst. for Digital Commun., Univ. of Edinburgh, Edinburgh, UK
fYear :
2010
fDate :
15-18 June 2010
Firstpage :
340
Lastpage :
345
Abstract :
In this paper, we present an efficient high-throughput threshold based sphere decoder (TSD) for multiple-input multiple-output (MIMO) systems. Depending on the instantaneous channel conditions, the proposed TSD compares the smallest singular value of the channel matrix with a predefined threshold on a frame-by-frame basis and switches between full expansion (FE) and partial expansion (PE) for the tree traversal to accelerate the detection procedure. The TSD has been implemented and validated on an FPGA platform and results indicate that the proposed decoder is very suitable for a highly-parallel and fully-pipelined hardware implementation. The proposed algorithm offers considerable throughput improvement over the original fixed-complexity sphere decoder (FSD) with only slightly increased resource use.
Keywords :
Clocks; Decoding; Field programmable gate arrays; Hardware; Iron; MIMO; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference on
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
978-1-4244-5887-5
Electronic_ISBN :
978-1-4244-5888-2
Type :
conf
DOI :
10.1109/AHS.2010.5546236
Filename :
5546236
Link To Document :
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