A new charge redistribution D/A and A/D converter technique pseudo C-2C ladder

Author

Cong, Lin ; Black, William C.

Author_Institution

Iowa State Univ., Ames, IA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

498

Abstract

C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of C-2C ladder restrict the linearity of the DAC. In this paper, a pseudo C-2C ladder structure is proposed. It compensates for the parasitic effect by adjusting the capacitor values in the ladders according to an optimization algorithm with further adjustments possible via an adaptive calibration method. Using this technique, a 3.3 V 9.2 mW 12-bit 1.4 MSPS successive approximation ADC was implemented in an HP0.5 μm single-poly triple-metal CMOS technology

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; circuit optimisation; digital-analogue conversion; ladder networks; 0.5 micron; 12 bit; 3.3 V; 9.2 mW; A/D converter; D/A converter; DAC architecture; HP single-poly triple-metal CMOS technology; adaptive calibration; charge redistribution; linearity; optimization algorithm; parasitic capacitance; pseudo C-2C ladder; successive approximation ADC; Approximation algorithms; CMOS technology; Capacitors; Energy consumption; Linearity; Mathematical model; Optimization methods; Parasitic capacitance; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951692

Filename

951692