• DocumentCode
    3503830
  • Title

    Design of die-pad on exposed substrate (DOES) leadframe package for DDR3 interface applications

  • Author

    Nansen Chen

  • Author_Institution
    MediaTek Inc., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    13-16 Aug. 2012
  • Firstpage
    567
  • Lastpage
    574
  • Abstract
    The fabless semiconductor companies always use the mature packages provided by the assembly houses. The cost and package selection trade-off shall be taken for different marketing segments. An innovative leadframe package was proposed with a cost competitiveness that increased more leads for digital TV applications compared to conventional leadframe package. The full channel from controller chip side to DRAM chip side was simulated and analyzed in the frequency and time domains. Results indicated that selection of proper ODT and drive strength achieves acceptable timing and voltage margins for DDR3 1350 Mb/s applications using the leadframe package on a two-layer PCB.
  • Keywords
    DRAM chips; assembling; electronics packaging; marketing; printed circuits; DDR3 interface applications; DOES leadframe package; DRAM chip side; assembly house; controller chip side; die-pad; exposed substrate; fabless semiconductor companies; innovative leadframe package; marketing segments; package selection; two-layer PCB; Abstracts; Digital TV; Lead; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4673-1682-8
  • Electronic_ISBN
    978-1-4673-1680-4
  • Type

    conf

  • DOI
    10.1109/ICEPT-HDP.2012.6474684
  • Filename
    6474684