Warpage analysis on package-on-package (PoP) for package stacking process

Since large warpage would make the solder ball not contact with the bond pad during reflow and induce open circuit, PoP Warpage becomes a main reliability issue in surface mount assembly. Differing from other researches, this study is focus on the SMT process effect on PoP warpage. A “displacement ratio” is adopted as a key factor for the comparison between two different assembly processes. A simplified finite element model is established for the numerical analysis. From the simulation results, it is found that if other conditions are same, the SMT process I (pre-stack one) will generate larger warpage. From the comparison of displacement ratio, the risk of open circuit in process I is higher.