Thermal analysis and heat dissipation optimization of 3D packaging with TSV interposer

In this paper, the finite element method (FEM) was used to simulate the thermal conduction in 2.5D IC integration with TSV (Through Silicon Via) interposer. The focus of the research is on the determination of the contributing factors and their effect on the temperature and heat distribution of the package. First, the steady thermal conduction of the package integrated with a chip power of 8W was computed with the initial design parameters. And then the relationship between the maximum temperature in the package and the chip power was investigated. The analysis illustrated that the thermal conductivity of EMC (Epoxy Molding Compound), BT substrate,under fill and the thickness of EMC are crucial for heat conduction in the package. Second, the parametric studies were performed to identify the effects of different parameters. Furthermore, the hot spot was analyzed and discussed. Also, a case for optimization for the design of heat dissipation was demonstrated and the guideline for thermal design for 2.5D integration was proposed.