• DocumentCode
    3504481
  • Title

    Study on the warpage and thermal stress in wire bonding and C4 stacked chip package

  • Author

    Gong Yu-bing ; Cen Chuan-sheng

  • Author_Institution
    Sch. of Mech. & Electr. Eng., Guilin Univ. of Electron. Technol., Guilin, China
  • fYear
    2012
  • fDate
    13-16 Aug. 2012
  • Firstpage
    720
  • Lastpage
    724
  • Abstract
    Stacked chip scale packaging has many good properties, such as higher packaging density, smaller signal delaying and better interconnection, which becomes one important technique of realizing 3D packaging. In this paper, the warpage and thermal stress of a three-chip stacked package which use wire-bonding connection and C4 connection during process was respectively analyzed and compared each other.
  • Keywords
    chip scale packaging; flip-chip devices; lead bonding; reflow soldering; thermal stresses; three-dimensional integrated circuits; 3D packaging; C4 flip-chip technology; C4 stacked chip package; packaging density; stacked chip scale packaging; thermal stress; warpage; wire bonding; Abstracts; Electromagnetic compatibility; Geometry; Stress; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4673-1682-8
  • Electronic_ISBN
    978-1-4673-1680-4
  • Type

    conf

  • DOI
    10.1109/ICEPT-HDP.2012.6474717
  • Filename
    6474717