Efficient Design of Multipliers for Pre-determined Coefficient Groups

Some digital signal processing applications, such as direct digital frequency synthesizer (DDFS), request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the CSD coding method, efficient multiplier design method for pre-determined coefficient groups is proposed. In the case of the multiplier of sine-cosine generator used in DDFS, it is shown that by the proposed method, area, power and delay time can be reduced by 53.13%, 45,59% and 22.64%, respectively, compared with conventional design. Also, in the case of pulse-shaping filter design used in CDMA, the area, power and delay time can be reduced by 47%, 42.3% and 38%, respectively