Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache

In embedded systems, handling time-critical real-time tasks is a challenge. The software may not only multi-task to improve response time, but also support events and interrupts, forcing the system to balance multiple priorities. Further, pre-emptive task switching hampers efficient interrupt processing, leading to instruction cache misses. This research provides a methodology for using software prefetch instructions in the interrupt handler to improve efficiency, thus making instruction caches more attractive in a real-time environment. The benefits of this technique are illustrated on an ARM processor running application benchmarks with different cache configurations and interrupt arrival patterns.