DocumentCode
3504766
Title
Real-Time Scheduling on Multicore Platforms
Author
Anderson, James H. ; Calandrino, John M. ; Devi, UmaMaheswari C.
Author_Institution
The University of North Carolina at Chapel Hill
fYear
2006
fDate
04-07 April 2006
Firstpage
179
Lastpage
190
Abstract
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power problems impose limits on the performance of single-core designs. Accordingly, several chip manufacturers have already released, or will soon release, chips with dual cores, and it is predicted that chips with up to 32 cores will be available within a decade. To effectively use the available processing resources on multicore platforms, software designs should avoid co-executing applications or threads that can worsen the performance of shared caches, if not thrash them. While cache-aware scheduling techniques for such platforms have been proposed for throughput-oriented applications, to the best of our knowledge, no such work has targeted real-time applications. In this paper, we propose and evaluate a cache-aware Pfair-based scheduling scheme for real-time tasks on multicore platforms
Keywords
Multicore architectures; multiprocessors; real-time; Application software; Computer architecture; Computer science; Job shop scheduling; Manufacturing; Multicore processing; Processor scheduling; Symbiosis; Throughput; Yarn; Multicore architectures; multiprocessors; real-time;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time and Embedded Technology and Applications Symposium, 2006. Proceedings of the 12th IEEE
ISSN
1545-3421
Print_ISBN
0-7695-2516-4
Type
conf
DOI
10.1109/RTAS.2006.35
Filename
1613334
Link To Document