• DocumentCode
    3506100
  • Title

    Reliability of fine pitch wafer level packages

  • Author

    Donglun Yang ; Xiaotong Ye ; Fei Xiao ; Dong Chen ; Li Zhang

  • Author_Institution
    Dept. of Mater. Sci., Fudan Univ., Shanghai, China
  • fYear
    2012
  • fDate
    13-16 Aug. 2012
  • Firstpage
    1097
  • Lastpage
    1101
  • Abstract
    Wafer level packaging (WLP) is regarded as one of the most potential single chip packages for its compatibility with wafer fabrication process. As the pitch size of the package becomes lower, the reliability of fine pitch WLP devices is greatly challenged. Finer pitch may result in weaker solder joints, which leads to reliability problems such as fatigue failure, creep deformation and so on. Much work has been done to investigate the reliability of wafer level package above 500 μm pitch under different conditions such as temperature cycling, thermal shock and drop test, etc. Nevertheless, there are few reports about the reliability of WLP with pitch size less than 500 μm. In this study, WLP with a size of 5×5 mm2 and a pitch of 400 μm were fabricated. Each chip has 144 lead-free SAC105 solder balls in an array of 12×12. The chips are reflowed on Ni/Au pads on boards. The chips were experienced a set of reliability tests including temperature cycling, thermal shock and drop test according to JEDEC standards. Furthermore, failure analysis is carried out to study the failure mechanism. Failures are found mostly inside of the solder ball after TC and TS tests, while the drop tests cause more damage to the solder-board and solder-chip interface.
  • Keywords
    copper alloys; failure analysis; gold alloys; nickel alloys; reliability; solders; tin alloys; wafer level packaging; JEDEC standards; SnAgCu; TC tests; TS tests; creep deformation; drop test; fatigue failure analysis; fine pitch wafer level package reliability; fme pitch WLP devices; lead-free SAC105 solder balls; single chip packages; solder-board interface; solder-chip interface; temperature cycling; thermal shock; wafer fabrication process; Abstracts; Fatigue; Lead; Reliability engineering; Semiconductor device reliability; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4673-1682-8
  • Electronic_ISBN
    978-1-4673-1680-4
  • Type

    conf

  • DOI
    10.1109/ICEPT-HDP.2012.6474799
  • Filename
    6474799