Title :
Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs
Author :
Hashimoto, Takashi ; Kumauchi, Takahiro ; Jinbo, Tomoko ; Watanabe, Kunihiko ; Yoshida, Eiichi ; Miura, Hideo ; Shiba, Takeo ; Tamaki, Yoichi
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fDate :
29 Sep-1 Oct 1996
Abstract :
The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affects crystallization process of amorphous-silicon to polysilicon, which results in a change of stress at the emitter layer
Keywords :
BiCMOS integrated circuits; VLSI; bipolar integrated circuits; doping profiles; elemental semiconductors; silicon; 0.3 micron; BiCMOS LSI; IDP process technology; Si; bipolar LSI; crystallization process; flat emitter region; hFE fluctuation control; high-speed ICs; polysilicon emitter; BiCMOS integrated circuits; Bipolar transistors; Crystallization; Fabrication; Fluctuations; Hydrogen; Laboratories; Large scale integration; Process control; Silicon;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1996., Proceedings of the 1996
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-3516-3
DOI :
10.1109/BIPOL.1996.554642
