• DocumentCode
    3506955
  • Title

    Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description

  • Author

    Howes, Lee W. ; Price, Paul ; Mencer, Oskar ; Beckmann, Olav ; Pell, Oliver

  • Author_Institution
    Imperial Coll. London, London
  • fYear
    2006
  • fDate
    28-30 Aug. 2006
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony´s Playstation 2 vector units offer scope for hardware acceleration of applications. We compare the performance of these architectures using a unified description based on A Stream Compiler (ASC) for FPGAs, which has been extended to target GPUs and PS2 vector units. Programming these architectures from a single description enables us to reason about optimizations for the different architectures. Using the ASC description we implement a Monte Carlo simulation, a fast Fourier transform (FFT) and a weighted sum algorithm. Our results show that without much optimization the GPU is suited to the Monte Carlo simulation, while the weighted sum is better suited to PS2 vector units. FPGA implementations benefit particularly from architecture specific optimizations which ASC allows us to easily implement by adding simple annotations to the shared code.
  • Keywords
    Monte Carlo methods; computer graphic equipment; coprocessors; electronic engineering computing; fast Fourier transforms; field programmable gate arrays; program compilers; ASC; Montecarlo simulation; Sony PlayStation 2 vector units; architecture specific optimizations; fast Fourier transform; field programmable gate arrays; graphics processing units; hardware acceleration; unified source description; weighted sum algorithm; Acceleration; Circuit synthesis; Computer architecture; Computer graphics; Coprocessors; Delay; Educational institutions; Field programmable gate arrays; Hardware; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
  • Conference_Location
    Madrid
  • Print_ISBN
    1-4244-0312-X
  • Type

    conf

  • DOI
    10.1109/FPL.2006.311203
  • Filename
    4100965