Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information

We present a framework for generating parameterised high-performance IP library cores from high level descriptions. Our system is based around the Quartz language which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design and compiling into parameterised VHDL libraries. We illustrate the application of our system to the design of several example circuits; placement constraints generated by our system can increase clock frequency by up to 25% and can also reduce area. Quartz placement information is flexible, allowing us to easily describe placed circuits which can be compacted when specialised for particular input values. We describe a self-specialising multiplier which adjusts component locations when some input bits are known; this multiplier can be easily integrated into larger circuits such as FIR filters or matrix multipliers