Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture

In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size.