Some results in automatic functional test design for VLSI circuits

This paper deals with the design and implementation of a universal functional test generator for VLSI circuits. Our approach to test generation - the functional test generation method - is based on knowledges and functional description of VLSI systems at functional VHDL level and the algorithm for automatic generation of test (normal executable test sequence of instructions) and arrangement, is used in very flexible and effective tool - functional test generation software system. Also a short methodology overview for the test synthesis of VLSI and ASIC circuits using an automated process of the VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG) is presented. The determination of the test efficiency of instructions mixes is discussed.