Fast Emulation of Permanent Faults in VLSI Systems

A confident use of deep-submicron VLSI systems requires the study of their behaviour in the presence of faults, which has been traditionally conducted via model-based fault injection techniques. Although field-programmable gate arrays (FPGAs) allows for a fast execution of models, its use to emulate the occurrence of permanent faults in VLSI models has been restricted so far to the well-known stuck-at fault model. Recent studies in fault representativeness point out the need of considering a wider set of faults modelling aspects like delays or short circuits. This paper presents new and different alternatives for the emulation of permanent faults. Several experiments have been performed using an automated tool that allows for the injection of all the studied fault models. Results from these experiments show both the feasibility of the proposed approach, and the time saving achieved by executing the models on FPGAs