Low voltage NexFET with record low figure of merit

A novel planar gate double-diffused MOS (DMOS) transistor is proposed for low voltage (<;10V) DC/DC converter and load switch applications. The novel MOSFET includes a heavily doped sinker layer in the JFET region and a field plate structure on the surface of the LDD region. The LDD region is fully depleted at a small drain bias, and the field plate acts as a shield electrode significantly reducing the gate to drain capacitance. The proposed MOSFET with a rating breakdown voltage of 12 V and a maximum gate voltage of 8 V demonstrates a specific on-resistance of 5.8 mΩ·mm² and a gate to drain charge of 0.4 nC/mm² at a gate voltage of 4.5 V. The corresponding figure of merit (FOM= R_{ON, sp}·Q_{gd, sp}) of the power MOSFET is 2.3 mΩ·nC, which is record low in the published literature.