On Reconfigurable Architectures for Efficient Matrix Inversion

This paper presents an analysis of the performance of the Gauss-Jordan matrix inversion algorithm on reconfigurable hardware platforms. The results show that currently available reconfigurable computing technology can already achieve significantly higher floating-point performance than CPUs for large matrices operations. For common reconfigurable systems, where the FPGAs are directly coupled to the on-board memory, the achievable performance scales directly with the number of realizable simultaneous memory accesses. A dedicated reconfigware architecture has been implemented and tested on a standard commercial reconfigurable platform. Even though the platform used had limited data bandwidth between the FPGA and the on-board memory, speed improvements of more than 3times have been observed, in comparison with software solutions running in high-end CPUs, for the inversion of matrices of orders up to 1700