Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs

As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a yield enhancement scheme based on the use of spare interconnect resources in each routing channel to tolerate functional faults. By using a node-covering technique and integer-linear programming (ILP) methods, the scheme is shown to provide minimal area and timing overheads. Significant yield improvements can thus be achieved.