DocumentCode
3507996
Title
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
Author
Ziener, Daniel ; Assmus, S. ; Teich, Jürgen
Author_Institution
Dept. of Comput. Sci., Erlangen-Nuremberg Univ., Erlangen, Germany
fYear
2006
fDate
28-30 Aug. 2006
Firstpage
1
Lastpage
6
Abstract
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This technique can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To identify a core, we compare the number of unique functions from lookup tables of the core with the lookup tables extracted from a product with an FPGA from an accused company. Also placement information can be used for increasing the reliability of the result. With these methods, no additional sources or information must be inquired from the accused company. These techniques can be used for netlist and bitfile cores, so a wide spectrum of cores can be identified.
Keywords
embedded systems; field programmable gate arrays; industrial property; logic design; security of data; table lookup; IP-core; Virtex-II Pro FPGA; Xilinx Virtex-II; lookup table content analysis; placement information; unlicensed usage; Computer science; Cryptography; Data mining; Data security; Embedded system; Field programmable gate arrays; Intellectual property; Protection; Table lookup; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location
Madrid
Print_ISBN
1-4244-0312-X
Type
conf
DOI
10.1109/FPL.2006.311255
Filename
4101017
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