Title :
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver
Author :
Herrero, Angel ; Jimenez-Pacheco, A. ; Caffarena, Gabriel ; Quirós, Javier Casajús
Author_Institution :
E.T.S.I. Telecomunicaciones, Univ. Politeenica de Madrid
Abstract :
In this paper we address the implementation on FPGAs of a 4G equaliser for a multiple-input multiple-output (MIMO) receiver. It is embedded in a multi-carrier code-division multiple-access (MC-CDMA) radio system, which is able to handle up to 32 users and provide transmission bit-rates up to 125 Mbps. We provide details on decisions taken for the design of the signal processing algorithm, including floating-point to fixed-point translation and architectural considerations. Implementation results using Xilinx Virtex-4 devices are finally reported
Keywords :
4G mobile communication; MIMO communication; code division multiple access; equalisers; field programmable gate arrays; 125 Mbit/s; 4G equalizer; Xilinx Virtex-4 devices; field programmable gate arrays; multi-carrier code-division multiple-access; multiple-input multiple-output receiver; Algorithm design and analysis; Baseband; Field programmable gate arrays; Hardware; MIMO; Multiaccess communication; Multicarrier code division multiple access; OFDM; Radio frequency; Receiving antennas;
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
DOI :
10.1109/FPL.2006.311309
