A study of fully silicided 0.18 /spl mu/m CMOS ESD protection devices

We studied the optimization of an ESD protection circuit based on MM and HBM test results using a test element group (TEG) created in a fully silicided 0.1 /spl mu/m CMOS process. We concluded that the change in drain area and channel width had different effects on the ESD robustness of different test items because the type of operating ESD protection element was determined by the polarity of the ESD surge applied. In addition, we found that, due to the formation of silicides in a source and drain contact, the dimensions around the contact had less influence on ESD robustness, while the channel width had a large influence on ESD robustness.