A study of fully silicided 0.18 /spl mu/m CMOS ESD protection devices

Author

Suzuki, Teruo ; Mitarai, Shin ; Ito, Seigo ; Monma, Hideo ; Higashi, Norikuni

Author_Institution

Fujitsu VLSI Ltd., Mie, Japan

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

78

Lastpage

87

Abstract

We studied the optimization of an ESD protection circuit based on MM and HBM test results using a test element group (TEG) created in a fully silicided 0.1 /spl mu/m CMOS process. We concluded that the change in drain area and channel width had different effects on the ESD robustness of different test items because the type of operating ESD protection element was determined by the polarity of the ESD surge applied. In addition, we found that, due to the formation of silicides in a source and drain contact, the dimensions around the contact had less influence on ESD robustness, while the channel width had a large influence on ESD robustness.

Keywords

CMOS integrated circuits; circuit optimisation; electrical contacts; electrostatic discharge; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; protection; surges; 0.18 micron; ESD protection circuit; ESD protection element; ESD robustness; ESD surge polarity; HBM test; MM test; channel width; contact dimensions; drain area; optimization; silicide formation; silicided CMOS ESD protection devices; silicided CMOS process; source/drain contact; test element group; test items; CMOS process; CMOS technology; Circuit testing; Electrostatic discharge; Large scale integration; Packaging; Protection; Robustness; Semiconductor devices; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.818993

Filename

818993