Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

Author

Voldman, Steven ; Hui, D. ; Warriner, L. ; Young, D. ; Howard, J. ; Assaderaghi, F. ; Shahidi, G.

Author_Institution

Div. for IBM Microelectron., IBM Corp., Essex Junction, VT, USA

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

105

Lastpage

115

Abstract

This paper discusses the electrostatic discharge (ESD) robustness of silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area.

Keywords

CMOS integrated circuits; aluminium; copper; electrostatic discharge; integrated circuit interconnections; integrated circuit metallisation; microprocessor chips; protection; semiconductor diodes; silicon-on-insulator; Al; Cu; ESD; ESD design area; ESD protection; ESD protection levels; ESD robustness; SOI CMOS technology; SOI microprocessors; Si-SiO/sub 2/; aluminum interconnects; copper interconnects; electrostatic discharge; lateral ESD SOI polysilicon-bound gated diodes; masking; microprocessor semiconductor chips; pin-count; process implants; semiconductor chips; silicon-on-insulator CMOS technology; Aluminum; CMOS technology; Capacitance; Electrostatic discharge; Insulation; MOSFET circuits; Microprocessors; Protection; Semiconductor films; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.818996

Filename

818996