DocumentCode :
3509635
Title :
High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures
Author :
Arce-Nazario, Rafael A. ; Jimenez, Manuel ; Rodríguez, Domingo
Author_Institution :
Puerto Rico Univ., Mayaguez
fYear :
2006
fDate :
28-30 Aug. 2006
Firstpage :
1
Lastpage :
4
Abstract :
This paper introduces a high-level partitioning methodology which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to multi-FPGA architectures. We review the global optimization scheme, the various methodology processes, and explain how their designs were influenced by characteristics of the discrete signal transforms and the target architecture. To illustrate our methodology´s solution quality, we present results of partitioning several FFT sizes to a Berkeley emulation engine 2 multi-FPGA module.
Keywords :
discrete transforms; fast Fourier transforms; field programmable gate arrays; logic partitioning; optimisation; FFT; discrete signal transforms; global optimization; high-level partitioning; multi-FPGA architectures; Computer architecture; Design methodology; Design optimization; Discrete transforms; Engines; Field programmable gate arrays; Optimization methods; Partitioning algorithms; Spirals; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
Conference_Location :
Madrid
Print_ISBN :
1-4244-0312-X
Type :
conf
DOI :
10.1109/FPL.2006.311341
Filename :
4101103
Link To Document :
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