High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures

This paper introduces a high-level partitioning methodology which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to multi-FPGA architectures. We review the global optimization scheme, the various methodology processes, and explain how their designs were influenced by characteristics of the discrete signal transforms and the target architecture. To illustrate our methodology´s solution quality, we present results of partitioning several FFT sizes to a Berkeley emulation engine 2 multi-FPGA module.