Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory

Author

Ikehashi, Tamio ; Imamiya, Kenichi ; Sakui, Koji

Author_Institution

MicroElectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

28-30 Sept. 1999

Firstpage

225

Lastpage

234

Abstract

With the use of a device simulator, we show that an ESD protection circuit whose junction is filled with contacts is suited to a scaled STI process with thin n/sup -/ junctions with n/sup +/ being implanted from contact holes. We have confirmed by measurements of the CMOS NAND flash memory that the protection has sufficient robustness.

Keywords

CMOS memory circuits; NAND circuits; circuit CAD; circuit simulation; doping profiles; electrostatic discharge; flash memories; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit reliability; isolation technology; protection; 256 Mbit; CMOS NAND flash memory; ESD protection circuit; ESD protection robustness; STI process NAND memory; contact holes; contact-filled junction; design methodology; device measurements; device simulator; n/sup +/ implant; robust ESD protection circuit; scaled STI process; thin n/sup -/ junctions; CMOS process; CMOS technology; Circuit simulation; Design methodology; Electrostatic discharge; Isolation technology; MOS devices; MOSFET circuits; Protection; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Conference_Location

Orlando, FL, USA

Print_ISBN

1-58637-007-X

Type

conf

DOI

10.1109/EOSESD.1999.819065

Filename

819065