• DocumentCode
    3509789
  • Title

    A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment

  • Author

    Bieser, Carsten

  • Author_Institution
    Inst. for Inf. Process. Technol., Karlsruhe Univ.
  • fYear
    2006
  • fDate
    28-30 Aug. 2006
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The novel platform concept and system design methodology the development process is shortened, which accelerates the complete design process and allows quick turn around times. For this, no knowledge of FPGA design or hardware description languages as VHDL or Verilog is necessary
  • Keywords
    field programmable gate arrays; hardware description languages; logic design; FPGA design acceleration; VHDL; Verilog; hardware description languages; system design methodology; system development; unique RP platform; Acceleration; Automotive engineering; Costs; Design engineering; Design methodology; Field programmable gate arrays; Hardware design languages; Libraries; Merging; Prototypes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2006. FPL '06. International Conference on
  • Conference_Location
    Madrid
  • Print_ISBN
    1-4244-0312-X
  • Type

    conf

  • DOI
    10.1109/FPL.2006.311350
  • Filename
    4101112
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3509789