High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic

The PhD project described in this paper aims to use word-length optimization techniques to automatically optimize the dynamic power consumption of high-level descriptions of DSP algorithms intended for implementation on FPGA, before or during synthesis. By developing models which can quickly estimate the power consumed by a system from a high-level description of the algorithm it implements, the author´s work allow for existing word-length optimization techniques to minimize the power consumption of a system, subject to acceptable signal distortion constraints