A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment

High-performance systems often require parallel processing of multiple data streams with strict timing constraints. With stringent system requirements, obtaining the highest performance is achieved by constructing specialized custom hardware - i.e. ASIC. However, when systems employ highly dynamic tasks that reflect various application requirements, the ASIC approach becomes very expensive because it needs to implement all task algorithms in hardware. Dynamically reconfigurable systems (DRS) can become a cost-effective solution by saving area and power through only loading currently requested and optimized tasks into a partially reconfigurable FPGA. This paper uses the framework of the DRS to effectively implement stream processing applications and to increase the cost-effectiveness of the DRS in a multi-task and multi-mode environment. The framework of the DRS describes virtual components (VCs) and the assembly mechanism to create cluster-specific system architecture