Noise measurements on Power4 Test chip

Author

Haridass, Anand ; James, Norman ; McCredie, Bradley

Author_Institution

IBM Corp., Austin, TX, USA

fYear

1999

fDate

1999

Firstpage

25

Lastpage

28

Abstract

This paper describes on-chip noise measured on the Power4 Test chip and its impact on the performance of clock and logic circuitry on the chip. It also summarizes the effect of on-module decoupling capacitors on the on-chip noise. The Power4 Test chip was fabricated in 0.1 μm effective channel length, 7 metal layer Cu, 1.5 V CMOS silicon-on-insulator technology. The test chip was designed to demonstrate technology feasibility and to facilitate chip and circuit design methodologies for the design of a 1 GHz microprocessor

Keywords

CMOS integrated circuits; capacitors; integrated circuit design; integrated circuit noise; integrated circuit testing; microprocessor chips; silicon-on-insulator; 0.1 micron; 1 GHz; 1.5 V; CMOS silicon-on-insulator technology; Cu; Cu metal layers; Power4 Test chip; Si-SiO₂; chip design methodologies; circuit design methodologies; clock circuit performance; effective channel length; logic circuit performance; microprocessor design; noise measurements; on-chip noise; on-module decoupling capacitors; technology feasibility; test chip design; CMOS logic circuits; CMOS technology; Circuit noise; Circuit testing; Clocks; Logic circuits; Logic testing; Noise measurement; Semiconductor device measurement; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5597-0

Type

conf

DOI

10.1109/EPEP.1999.819186

Filename

819186