On-chip wiring design challenges for GHz operation

Author

Deutsch, A. ; Smith, H. ; Kopcsay, G.V. ; Edelstein, D.C. ; Coteus, P.W.

Author_Institution

Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1999

fDate

1999

Firstpage

45

Lastpage

48

Abstract

This presentation reviews current on-chip wiring design practices and the fundamental properties of on-chip lossy transmission lines. The deficiencies of RC-circuit representation are highlighted and it is shown that many of the modeling and simulation techniques developed for package interconnections must be adopted by microprocessor designers in order to achieve GHz clock rates

Keywords

circuit simulation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; losses; microprocessor chips; RC-circuit representation; clock rates; microprocessor design; modeling techniques; on-chip lossy transmission lines; on-chip wiring design; on-chip wiring design practices; package interconnections; simulation techniques; Circuit noise; Clocks; Crosstalk; Driver circuits; Integrated circuit interconnections; Packaging; Propagation delay; RLC circuits; System-on-a-chip; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5597-0

Type

conf

DOI

10.1109/EPEP.1999.819190

Filename

819190