Title :
Impact of cross-over lines on delay time of two parallel global wires [IC interconnects]
Author :
Kim, Sangwoo ; Chang, Chi Shih ; Neikirk, Dean P.
Author_Institution :
Sematech, Austin, TX, USA
Abstract :
The length of the address or data lines between the ALU and cache sections on a microprocessor chip may exceed 10 mm. To minimize the delay time impact due to the signal line series resistance, one may use the 2×2 μm2 lines on the M7 and/or M8 layers for the address and data buses. We investigate the delay time impact due to the series resistance for two coupled lines on M7, including the influence of the cross-over lines on the M6 and M8 layers. The cross-over lines on M6 and M8 cause increase in self-capacitance and reduction in mutual-capacitance for two adjacent address lines on M7. The delay time of the address or data information, in +/+ and +/- configurations, is affected differently for different line length
Keywords :
cache storage; capacitance; delays; electric resistance; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; microprocessor chips; ALU section; IC interconnects; address buses; address lines; adjacent address lines; cache section; coupled lines; cross-over lines; data buses; data lines; delay time; line length; metal layers; microprocessor chip; mutual-capacitance; parallel global wires; self-capacitance; series resistance; signal line series resistance; Attenuation; Capacitance; Couplings; Delay effects; Delay lines; Drives; Frequency dependence; Inductance; Surface impedance; Wires;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5597-0
DOI :
10.1109/EPEP.1999.819192
