Power distribution modeling and decoupling of multilayer printed circuit board

Author

Bandyopadhyay, J.

Author_Institution

IBM Corp., Austin, TX

fYear

1999

fDate

1999

Firstpage

103

Lastpage

106

Abstract

Determining the proper number and value of decoupling capacitors for boards/cards is always a challenging issue for board/card designers. Lack of proper analysis leads to either conservative or aggressive design. This paper presents a methodology for determining the right number and location of decoupling capacitors for a card/board through detailed board modeling. An example has been provided to demonstrate the effect of decoupling capacitors in reducing induced dI/dt noise for a multilayer CPU card with PowerPCT^TM processor used in IBM´s RS/6000 machine

Keywords

capacitors; circuit noise; integrated circuit packaging; microprocessor chips; power supply circuits; printed circuit design; IBM RS/6000 machine; PowerPCT processor; board design; board modeling; decoupling; decoupling capacitor location; decoupling capacitors; multilayer CPU card; multilayer printed circuit board; power distribution modeling; simultaneous switching noise; CMOS technology; Capacitors; Frequency; Low-frequency noise; Nonhomogeneous media; Packaging; Power distribution; Power system modeling; Printed circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5597-0

Type

conf

DOI

10.1109/EPEP.1999.819203

Filename

819203