DocumentCode
3511022
Title
Design and performance evaluation of chip capacitors on microprocessor packaging
Author
Yew, Teong-Guan ; Li, Yuan-Liang ; Chung, Chee-Yee ; Figueroa, David G.
Author_Institution
Intel Corp., Chandler, AZ, USA
fYear
1999
fDate
1999
Firstpage
175
Lastpage
178
Abstract
This paper describes the different chip capacitor placement design on Intel´s latest Celeron CPU package. The evaluation of its effectiveness in the power delivery network and final impact on CPU performance are also discussed
Keywords
capacitors; driver circuits; integrated circuit design; integrated circuit packaging; microprocessor chips; CPU performance; Intel Celeron CPU package; chip capacitor effectiveness; chip capacitor placement design; chip capacitors; microprocessor packaging; performance evaluation; power delivery network; Capacitors; Costs; Electronics packaging; Frequency; Inductance; Microprocessors; Noise reduction; Performance analysis; Plastic packaging; Predictive models;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5597-0
Type
conf
DOI
10.1109/EPEP.1999.819220
Filename
819220
Link To Document