• DocumentCode
    3511808
  • Title

    Hierarchical modeling and verification of embedded systems

  • Author

    Cortés, Luis Alejandro ; Eles, Petru ; Peng, Zebo

  • Author_Institution
    Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    63
  • Lastpage
    70
  • Abstract
    In order to represent efficiently large systems, a mechanism for hierarchical composition is needed so that the model may be constructed in a structured manner and composed of simpler units easily comprehensible by the designer at each description level. In this paper we formally define the notion of hierarchy for a Petri net based representation used for modeling embedded systems. We show how small parts of a large system may be transformed by using the concept of hierarchy and the advantages of a transformational approach in the verification of embedded systems. A real-life example illustrates the feasibility of our approach on practical applications
  • Keywords
    embedded systems; formal specification; Petri net; embedded systems; hierarchical modeling; hierarchical verification; real-life example; Computational modeling; Data flow computing; Embedded computing; Embedded system; Flow graphs; Information science; Petri nets; Process design; Real time systems; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
  • Conference_Location
    Warsaw
  • Print_ISBN
    0-7695-1239-9
  • Type

    conf

  • DOI
    10.1109/DSD.2001.952119
  • Filename
    952119