Title :
Investigation of lateral charge distribution of 2-bit SONOS memory devices using physically separated twin SONOS structure
Author :
Choi, Byung Yong ; Lee, Choong-Ho ; Lee, Yong Kyu ; Shin, Hyungcheol ; Lee, Jong Duk ; Park, Byung-Gook ; Kim, Dong-Won ; Sung, Suk-Kang ; Lee, Se Hoon ; Cho, Byung-Kyu ; Kim, Tae-Yong ; Cho, Eun Suk ; Lee, Jong Jin ; Park, Donggun
Author_Institution :
ISRC & Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
Abstract :
The lateral charge distribution on 2-bit SONOS memory can be readily characterized using physically separated twin SONOS structure. The damascene gate and outer sidewall process successfully contribute to make the twin SONOS structure down to 80nm gate regime. Its lateral charge distribution is estimated through the SS and Vth shifts for forward and reverse reading and confirmed by the comparison with a conventional (non-separated) SONOS structure.
Keywords :
integrated memory circuits; semiconductor-insulator-semiconductor devices; 2 bit; 80 nm; SONOS memory devices; damascene gate; lateral charge distribution; outer sidewall process; twin SONOS structure; Channel hot electron injection; Charge carrier processes; Computer science; Current measurement; Degradation; Fabrication; Hot carriers; Process control; SONOS devices; Size control;
Conference_Titel :
Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on
Print_ISBN :
1-4244-0167-4
DOI :
10.1109/ICMTS.2006.1614273
