On the passivation of interface states in SONOS test structures: impact of device layout and annealing process

Author

Driussi, F. ; Selmi, L. ; Akil, N. ; van Duuren, M.J. ; van Schaijk, R.

Author_Institution

DIEGM, Udine Univ., Italy

fYear

2006

fDate

6-9 March 2006

Firstpage

51

Lastpage

55

Abstract

This paper reports the experimental evidence of anomalous electrical characteristics of large test structures for the characterization of SONOS gate stacks. The anomaly is studied on devices featuring different layout and it is attributed to the property of silicon nitride to block the hydrogen anneal and the passivation of the Si/SiO₂ interface dangling bonds. Since the hydrogen passivation can occur only from the lateral sides of the device, our findings imply restrictions on the dimensions and on the layout of the test structures used to study the electrical properties of SONOS devices.

Keywords

annealing; elemental semiconductors; interface states; passivation; semiconductor-insulator-semiconductor structures; silicon; silicon compounds; SONOS devices; SONOS gate stacks; Si-SiO₂; annealing process; device layout; electrical properties; hydrogen passivation; interface dangling bonds; Annealing; Capacitance; Distortion measurement; Hydrogen; Interface states; MOS capacitors; Passivation; SONOS devices; Silicon; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2006. ICMTS 2006. IEEE International Conference on

Print_ISBN

1-4244-0167-4

Type

conf

DOI

10.1109/ICMTS.2006.1614274

Filename

1614274