• DocumentCode
    3512681
  • Title

    Integration of power semiconductors devices: Synchronous buck converters in a package

  • Author

    Herbsommer, Juan A. ; Noquil, J. ; Lopez, O. ; Sherman, J.

  • Author_Institution
    Texas Instrum., Bethlehem, PA, USA
  • fYear
    2012
  • fDate
    5-9 Feb. 2012
  • Firstpage
    1705
  • Lastpage
    1707
  • Abstract
    Integration in power semiconductor devices has been always a challenge for technologists. This occurs mainly because the integration process increases the power density with negative consequences in the temperature of the devices which deteriorate the electrical and reliability performance in comparison with discrete approach. In order to successfully integrate power microelectronic devices one needs to have semiconductor solutions with extremely good efficiency to dissipate small quantities of heat and package solutions that can conduct extremely well the heat generated so the junction temperature of the device does not exceed the maximum temperatures under specifications. Traditional approaches to improve efficiency in DC/DC synchronous buck converters include reducing conduction losses in the MOSFETs through lower RDS(ON) devices and lowering switching losses through low-frequency operation. However the incremental improvements in RDS(ON) are at a point of diminishing returns and low RDS(ON) devices have large parasitic capacitances that do not facilitate the high-frequency operation required to improve power density. The drive for higher efficiency and excellent thermal performance to achieve high degree of integration is being addressed by advancements in both silicon and packaging technologies. In this paper we present the Power Stage concept, the technology we developed in the silicon and packaging fronts in order to integrate a half bridge DC-DC synchronous Buck converter with a gate driver IC. The NexFET Power Stage achieves higher levels of performance and integration, and in half the space versus discrete MOSFETs. This article explains these new technologies and highlights their performance advantage.
  • Keywords
    DC-DC power convertors; power MOSFET; semiconductor device packaging; semiconductor device reliability; conduction loss reduction; discrete MOSFET; gate driver IC; half bridge DC-DC synchronous buck converter; heat solution; junction temperature generation; lower RDS(ON) device; nexFET power stage concept; packaging technology; parasitic capacitance; power density; power microelectronic device integration; power semiconductor device integration; switching loss; thermal performance; Copper; Integrated circuits; Junctions; Logic gates; MOSFETs; Performance evaluation; Temperature measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    978-1-4577-1215-9
  • Electronic_ISBN
    978-1-4577-1214-2
  • Type

    conf

  • DOI
    10.1109/APEC.2012.6166051
  • Filename
    6166051