VLSI implementation of an effective lattice reduction algorithm with fixed-point considerations

Lattice reduction-aided equalization techniques have emerged as a low-complexity method to achieve the same diversity as maximum likelihood detectors. We address the VLSI implementation of these LR-aided equalizers by modifying the CLLL algorithm from a fixed-point hardware perspective. We then apply the modified algorithm together with additional micro-architecture and operation scheduling enhancements to create an updated CLLL processor. Finally, through BER simulations and FPGA synthesis results we demonstrate the suitability of our CLLL processor for integration into a 64-QAM MIMO system.